RSS
Real-time operating systems
- INTEGRITY RTOS for Application Processors
The totally reliable and absolutely secure operating system. Certified at the highest levels of safety for automotive, industrial and railway. - µ-velOSity RTOS for Microcontrollers
Small, fast, easy-to-use. Certified at the highest levels of safety for automotive, industrial and railway.
Software Development tools
- MULTI Development Environment
- Quickly find and fix bugs and bottlenecks on heterogenous multicore systems
- Display system events, CPU performance, call stacks and more on the intuitive timeline GUI of History® system viewer
- Debug backward in time with TimeMachine®
- Easily share debug results and states with Debug Snapshot™
- Green Hills Optimizing Compilers
Generate the smallest and fastest code from C, C++. Certified for the highest levels of functional safety.
Processor Probes
- Green Hills Probe V4
For multicore hardware bring-up, low-level debugging, and trace-powered analysis tools.
A complete offering for developing and deploying RISC-V applications
Architecture-specific support for RISC-V
The Green Hills C/C++ Optimizing Compilers for RISC-V bring the following key features to the RISC-V architecture:
- Certified at highest safety levels for Automotive (ISO 26262), Industrial (IEC 61508) and Railway (EN 50128/50657)
- Support for a comprehensive list of ISA modules
- Both 32-bit and 64-bit RISC-V architectures are supported
- Compiler and debugger support for custom instructions
- Decades of industry-leading experience in C/C++ compiler technology that generates the fastest, smallest, and most reliable code
The RISC-V instruction set architecture is modular and extensible, allowing designers to include only the instruction set modules they require, and to incorporate their own custom instructions. Green Hills C/C++ Compilers and tool chain support the following ISA base and extensions, enabling developers to choose the exact instruction set modules required for compiling their code.
RISC-V custom instructions
A popular feature of the open RISC-V architecture is that users can incorporate their own custom instructions into their design. The Green Hills development tools offer an easy way to add new instructions into the compiler, assembler, MULTI debugger, and instruction set simulator.
Supported instruction set modules
| • | A | Atomic instructions |
| • | B | Bit manipulation |
| • | C | Compressed instruction set |
| • | D, F | Single and double precision floating point |
| • | G | Shorthand for IMAFD Zicsr Zifencei |
| • | H | Hypervisor |
| • | I | Base integer unit |
| • | M | Integer multiplication and division |
| • | P | Packed SIMD instructions (planned, not ratified) |
| • | Q | Quad-precision floating-point (assembly support only) |
| • | S | Supervisor-level - Svinval, Sstc, Svnapot, Svpbmt |
| • | V | Vector extensions (assembly and simulation support only) |
| • | Zb… | Additional bit manipulation instructions |
| • | Zc… | Compressed instruction set sub-extensions |
| • | Zdinx, Zfinx, Zhinx… | Floating point in integer registers: Single-precision, Double-precision, Half-precision, Minimal half-precision |
| • | Zfa | Additional floating-point instructions |
| • | Zfh, Zfhmin | Half-precision and Minimal half-precision floating-point |
| • | Zicsr, Zifencei | Enabled by default with I |
| • | Zicntr, Zihpm | Base counters, timers, and hardware performance counters |
| • | Zihintpause | Pause hint instruction |
| • | Zvl… | Minimum vector register lengths (VLEN) |
| • | Zvamo, Zvlsseg | Additional vector support for AMO operations and load/store segment instructions |
| • | Zve … | Vector extensions for embedded processors, enabling a subset of V |
Additionally, RISC-V includes a separate privileged instruction set specification. These privileged instructions are supported. Pre-built runtime libraries are provided for compatibility with all of these configurations.
